Trench shielding structure for semiconductor device and method

ABSTRACT

A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of U.S. application Ser. No.12/271,068 entitled TRENCH SHIELDING STRUCTURE FOR SEMICONDUCTOR DEVICEAND METHOD filed Nov. 14, 2008, which is incorporated herein byreference in its entirety to provide continuity of disclosure.

FIELD OF THE INVENTION

This document relates generally to semiconductor devices, and morespecifically to insulated gate structures and methods of formation.

BACKGROUND OF THE INVENTION

Metal oxide field effect transistor (MOSFET) devices are used in manypower switching applications such as dc-dc converters. In a typicalMOSFET, a gate electrode provides turn-on and turn-off control with theapplication of an appropriate gate voltage. By way of example, in ann-type enhancement mode MOSFET, turn-on occurs when a conductive n-typeinversion layer (i.e., channel region) is formed in a p-type body regionin response to the application of a positive gate voltage, which exceedsan inherent threshold voltage. The inversion layer connects n-typesource regions to n-type drain regions and allows for majority carrierconduction between these regions.

There is a class of MOSFET devices where the gate electrode is formed ina trench that extends downward from a major surface of a semiconductormaterial such as silicon. Current flow in this class of devices isprimarily vertical and, as a result, device cells can be more denselypacked. All else being equal, this increases the current carryingcapability and reduces on-resistance of the device.

In certain applications, high frequency switching characteristics areimportant and certain design techniques have been used to reducecapacitive effects thereby improving switching performance. By way ofexample, it is previously known to incorporate an additional electrodebelow the gate electrode in trench MOSFET devices and to connect thisadditional electrode to the source electrode or another bias source.This additional electrode is often referred to as a “shield electrode”and functions, among other things, to reduce gate-to-drain capacitance.Shield electrodes have been previously used as well in planar MOSFETdevices.

Although shield electrodes improve device performance, challenges stillexist to more effectively integrate them with other device structures.These challenges include avoiding additional masking steps, addressingnon-planar topographies, and avoiding excessive consumption of die area.These challenges impact, among other things, cost and manufacturability.Additionally, opportunities exist to provide devices having shieldelectrodes with more optimum and reliable performance.

Accordingly, structures and methods of manufacture are needed toeffectively integrate shield electrode structures with other devicestructures and to provide more optimum and reliable performance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a partial cross-sectional view of a first embodimentof a semiconductor structure taken along reference line I-I of FIG. 2;

FIG. 2 illustrates a top plan view of a first embodiment of asemiconductor device including the structure of FIG. 1;

FIG. 3 illustrates a top plan view of a second embodiment of asemiconductor device;

FIG. 4 illustrates a partial cross-sectional view of a portion of thesemiconductor device of FIG. 2 taken along reference line IV-IV;

FIGS. 5-16 illustrate partial cross-sectional views of the portion ofFIG. 4 at various stages of fabrication;

FIG. 17 illustrates a partial top plan view of a contact structure inaccordance with a first embodiment;

FIG. 18 illustrates a partial top plan view of a contact structure inaccordance with a second embodiment;

FIG. 19 illustrates a partial top plan view of a contact structure inaccordance with a third embodiment;

FIG. 20 illustrates a partial top plan view of the semiconductor deviceof FIG. 2 including a first embodiment of a shielding structure;

FIG. 21 illustrates a cross-sectional view of the shielding structure ofFIG. 20 taken along reference line XXI-XXI;

FIG. 22 illustrates a partial top plan view of the semiconductor deviceof FIG. 2 including a second embodiment of a shielding structure;

FIG. 23 illustrates a partial top plan view of the semiconductor deviceof FIG. 2 including a third embodiment of a shielding structure;

FIG. 24 illustrates a partial top plan view of a portion of thesemiconductor device of FIG. 2; and

FIG. 25 illustrates a cross-sectional view of another embodiment of asemiconductor device.

For simplicity and clarity of illustration, elements in the figures arenot necessarily drawn to scale, and the same reference numbers indifferent figures denote generally the same elements. Additionally,descriptions and details of well-known steps and elements may be omittedfor simplicity of the description. As used herein current-carryingelectrode means an element of a device that carries current through thedevice such as a source or a drain of an MOS transistor or an emitter ora collector of a bipolar transistor or a cathode or anode of a diode,and a control electrode means an element of the device that controlscurrent through the device such as a gate of a MOS transistor or a baseof a bipolar transistor. Although the devices are explained herein ascertain N-channel devices, a person of ordinary skill in the art willappreciate that P-channel devices and complementary devices are alsopossible in accordance with the present description. For clarity of thedrawings, doped regions of device structures are illustrated as havinggenerally straight-line edges and precise angular corners. However,those skilled in the art understand that due to the diffusion andactivation of dopants, the edges of doped regions are generally notstraight lines and the corners are not precise angles.

In addition, structures of the present description may embody either acellular base design (where the body regions are a plurality of distinctand separate cellular or stripe regions) or a single base design (wherethe body region is a single region formed in an elongated pattern,typically in a serpentine pattern or a central portion with connectedappendages). However, one embodiment of the present description will bedescribed as a cellular base design throughout the description for easeof understanding. It should be understood that it is intended that thepresent disclosure encompass both a cellular base design and a singlebase design.

DETAILED DESCRIPTION OF THE DRAWINGS

In general, the present description pertains to a shielding structurefor a semiconductor device. In one embodiment, the shielding structureis formed in a plurality of closely spaced trenches and includes aninsulator layer, a shield electrode in each trench and an interlayerdielectric overlying the trenches. In one embodiment, the shieldelectrodes are configured to be connected to a ground potential. In oneembodiment, the shielding structure is placed beneath at least a portionof a control pad structure. In another embodiment, the shieldingstructure is placed beneath at least a portion of a control runnerconfiguration.

FIG. 1 shows a partial cross-sectional view of a semiconductor device orcell 10 having a shield electrode or electrodes 21. The cross-section istaken, for example, along reference line I-I from active area 204 ofdevice 20 shown in FIG. 2. In this embodiment, device 10 comprises aMOSFET structure, but it is understood that this description applies aswell to insulated gate bipolar transistors (IGBT), MOS-gated thyristors,and the like.

Device 10 includes a region of semiconductor material, semiconductormaterial, or semiconductor region 11, which comprises for example, ann-type silicon substrate 12 having a resistivity in a range from about0.001 ohm-cm to about 0.005 ohm-cm. Substrate 12 can be doped withphosphorous or arsenic. In the embodiment shown, substrate 12 provides adrain contact or a first current carrying contact for device 10. Asemiconductor layer, drift region, or extended drain region 14 is formedin, on, or overlying substrate 12. In one embodiment, semiconductorlayer 14 is formed using conventional epitaxial growth techniques.Alternatively, semiconductor layer 14 is formed using conventionaldoping and diffusion techniques. In an embodiment suitable for a 50 voltdevice, semiconductor layer 14 is n-type with a dopant concentration ofabout 1.0×10¹⁶ atoms/cm³ and has a thickness from about 3 microns toabout 5 microns. The thickness and dopant concentration of semiconductorlayer 14 is increased or decreased depending on the desireddrain-to-source breakdown voltage (BVDss) rating of device 10. It isunderstood that other materials may be used for semiconductor material11 or portions thereof including silicon-germanium,silicon-germanium-carbon, carbon-doped silicon, silicon carbide, or thelike. Additionally, in an alternate embodiment, the conductivity type ofsubstrate 12 is switched to be opposite the conductivity type ofsemiconductor layer 14 to form, for example, an IGBT embodiment.

Device 10 also includes a body, base, PHV, or doped region or regions 31extending from a major surface 18 of semiconductor material 11. Bodyregions 31 have a conductivity type that is opposite to the conductivitytype of semiconductor layer 14. In this example, body regions 31 arep-type conductivity. Body regions 31 have a dopant concentrationsuitable for forming inversion layers that operate as conductionchannels or channel regions 45 of device 10. Body regions 31 extend frommajor surface 18 to a depth, for example, from about 0.5 microns toabout 2.0 microns. N-type source regions, current conducting regions, orcurrent carrying regions 33 are formed within, in, or overlying bodyregions 31 and extend from major surface 18 to a depth, for example,from about 0.1 microns to about 0.5 microns. A p-type body contact orcontact region 36 can be formed in body regions 31, and is configured toprovide a lower contact resistance to body regions 31.

Device 10 further includes trench control, trench gate, or trenchstructures 19, which extend in a substantially vertical direction frommajor surface 18. Alternatively, trench control structures 19 orportions thereof have a tapered shape. Trench structures 19 includetrenches 22, which are formed in semiconductor layer 14. For example,trenches 22 have a depth from about 1.5 microns to about 2.5 microns ordeeper. In one embodiment, trenches 22 extend all the way throughsemiconductor layer 14 into substrate 12. In another embodiment,trenches 22 terminate within semiconductor layer 14.

Passivating layers, insulator layers, field insulator layers or regions24 are formed on lower portions of trenches 22 and comprise, forexample, an oxide, a nitride, combinations thereof, or the like. In oneembodiment, insulator layers 24 are silicon oxide and have a thicknessfrom about 0.1 microns to about 0.2 microns. Insulator layers 24 can beuniform in thickness or variable thickness. Additionally, the thicknessof layer 24 may be varied, depending on the desired drain-to-sourcebreakdown voltage (BVDss). Shield electrodes 21 are formed overlyinginsulator layers 24 in substantially centrally located lower portions oftrenches 22. In one embodiment, shield electrodes 21 comprisepolycrystalline semiconductor material that can be doped. In anotherembodiment, shield electrodes 21 can comprise other conductivematerials. In contact structure embodiments described below, portions oftrenches 22 in the contact structure areas have insulator layers 24along upper sidewall portions as well.

Passivating, dielectric, or insulator layers 26 are formed along uppersidewall portions of trenches 22 and are configured as gate dielectricregions or layers. By way of example, insulator layers 26 compriseoxide, nitride, tantalum pentoxide, titanium dioxide, barium strontiumtitanate, combinations thereof, or the like. In one embodiment,insulator layers 26 are silicon oxide and have a thickness from about0.01 microns to about 0.1 microns. In one embodiment, insulator layers24 are thicker than insulator layers 26. Passivating, dielectric, orinsulator layers 27 are formed overlying shield electrodes 21, and inone embodiment insulator layers 27 have a thickness between thethickness of insulator layers 24 and insulator layers 26. In oneembodiment, insulator layers 27 have a thickness greater than thethickness of insulator layer 26, which improves oxide breakdown voltageperformance.

Trench structures 19 further include control electrodes or gateelectrodes 28, which are formed overlying insulator layers 26 and 27. Inone embodiment, gate electrodes 28 comprise doped polycrystallinesemiconductor material such as polysilicon doped with an n-type dopant.In one embodiment, trench structures 19 further include a metal orsilicide layer 29 formed adjoining gate electrode 28 or upper surfacesthereof. Layer 29 is configured to reduce gate resistance.

An interlayer dielectric (ILD), dielectric, insulator, or passivatinglayer 41 is formed overlying major surface 18 and above trenchstructures 19. In one embodiment, dielectric layer 41 comprises asilicon oxide and has a thickness from about 0.4 microns to about 1.0micron. In one embodiment, dielectric layer 41 comprises a depositedsilicon oxide doped with phosphorous or boron and phosphorous. In oneembodiment, dielectric layer 41 is planarized to provide a more uniformsurface topography, which improves manufacturability.

Conductive regions or plugs 43 are formed through openings or vias indielectric layer 41 and portions of semiconductor layer 14 to providefor electrical contact to source regions 33 and body regions 31 throughcontact regions 36. In one embodiment, conductive regions 43 areconductive plugs or plug structures. In one embodiment, conductiveregions 43 comprise a conductive barrier structure or liner plus aconductive fill material. In one embodiment, the barrier structureincludes a metal/metal-nitride configuration such astitanium/titanium-nitride or the like. In another embodiment, thebarrier structure further includes a metal-silicide structure. In oneembodiment, the conductive fill material includes tungsten. In oneembodiment, conductive regions 43 are planarized to provide a moreuniform surface topography.

A conductive layer 44 is formed overlying major surface 18 and aconductive layer 46 is formed overlying a surface of semiconductormaterial 11 opposite major surface 18. Conductive layers 44 and 46 areconfigured to provide electrical connection between the individualdevice components of device 10 and a next level of assembly. In oneembodiment, conductive layer 44 istitanium/titanium-nitride/aluminum-copper or the like and is configuredas a source electrode or terminal. In one embodiment, conductive layer46 is a solderable metal structure such as titanium-nickel-silver,chromium-nickel-gold, or the like and is configured as a drain electrodeor terminal. In one embodiment, a further passivation layer (not shown)is formed overlying conductive layer 44. In one embodiment, shieldelectrodes 21 are connected (in another plane) to conductive layer 44 sothat shield electrodes 21 are configured to be at the same potential assource regions 33 when device 10 is in use. In another embodiment,shield electrodes 21 are configured to be independently biased.

In one embodiment, the operation of device 10 proceeds as follows.Assume that source electrode (or input terminal) 44 and shieldelectrodes 21 are operating at a potential V_(S) of zero volts, gateelectrodes 28 receive a control voltage V_(G) of 2.5 volts, which isgreater than the conduction threshold of device 10, and drain electrode(or output terminal) 46 operates at a drain potential VD of 5.0 volts.The values of V_(G) and V_(S) cause body region 31 to invert adjacentgate electrodes 28 to form channels 45, which electrically connectsource regions 33 to semiconductor layer 14. A device current I_(DS)flows from drain electrode 46 and is routed through source regions 33,channels 45, and semiconductor layer 14 to source electrode 44. In oneembodiment, I_(DS) is on the order of 1.0 amperes. To switch device 10to the off state, a control voltage V_(G) of less than the conductionthreshold of device 10 is applied to gate electrodes 28 (e.g., V_(G)<2.5volts). This removes channels 45 and I_(DS) no longer flows throughdevice 10.

Shield electrodes 21 are configured to control the width of thedepletion layer between body region 31 and semiconductor layer 14, whichenhances source-to-drain breakdown voltage. Also, shield electrodes 21help reduce gate-to-drain charge of device 10. Additionally, becausethere is less overlap of gate electrode 28 with semiconductor layer 14compared to other structures, the gate-to-drain capacitance of device 10is reduced. These features enhance the switching characteristics ofdevice 10.

FIG. 2 shows a top plan view of a semiconductor device, die or chip 20that includes device 10 of FIG. 1. For perspective, FIG. 2 is generallylooking down at major surface 18 of semiconductor material 11 shown inFIG. 1. In this embodiment, device 20 is bounded by a die edge 51, whichcan be the center of a scribe line used to separate chip 20 from otherdevices when in wafer form. Device 20 includes a control pad, gate metalpad or gate pad 52, which is configured to electrically contact gateelectrodes 28 (shown in FIG. 1) through gate metal runners or gaterunners or feeds 53, 54, and 56. In this embodiment, gate metal pad 52is placed in a corner portion 238 of device 20. In one embodiment, gaterunner 54 is adjacent to an edge 202 of device 20, and gate runner 56 isadjacent another edge 201 of device 20, which is opposite to edge 202.In one embodiment, trenches 22 extend in a direction from edge 201 toedge 202. In one embodiment, central portion 203 of device 20 is absentany gate runner(s). That is, in one embodiment the gate runners areplaced in only peripheral or edge portions of device 20.

Conductive layer 44, which is configured in this embodiment as a sourcemetal layer, is formed over active portions 204 and 206 of device 20. Inone embodiment, portion 444 of conductive layer 44 wraps around endportion 541 of gate runner 54. A portion 446 of conductive layer 44wraps around end portion 561 of gate runner 56 and is designated asstructure 239. Structure 239 is further shown in more detail in FIG. 24.Conductive layer 44 is further configured to form shield electrodecontacts, runners, or feeds 64 and 66, which in this embodiment providecontact to shield electrodes 21. In this configuration, conductive layer44 is connected to shield electrodes 21. In the wrap aroundconfiguration described above, conductive layer 44, portions 444 and446, shield electrode runners 64 and 66 and gate runners 54 and 56 arein the same plane and do not overlap each other. This configurationprovides for the use of a single metal layer, which simplifiesmanufacturing.

In one embodiment, shield electrode runner 66 is placed between edge 201of device 20 and gate runner 56, and shield electrode runner 64 isplaced between edge 202 of device 20 and gate runner 54. In oneembodiment, additional contact is made to shield electrodes 21 in shieldcontact region, contact region or stripe 67, which separates the activearea of device 20 into portions 204 and 206. Contact region 67 isanother location on device 20 where contact between conductive layer 44and shield electrodes 21 are made. Contact region 67 is configured todivide gate electrodes 28 into two portions within device 20. The twoportions include one portion that feeds from gate runner 54 and anotherportion that feeds from gate runner 56. In this configuration, gateelectrode material 28 is absent from contact region 67. That is, gateelectrodes 28 do not pass through contact region 67.

In embodiments that place gate pads 52 in a corner (e.g., corner 23) ofdevice 20, the effects of gate resistance can be more optimallydistributed through a selected or predetermined placement of contactregion 67 within device 20. This predetermined placement provides moreuniform switching characteristics. In one embodiment, contact region 67is offset from center 203 so that contact region 67 is closer to edge202 than edge 201 with gate pad 52 in corner portion 238 adjacent toedge 201. That is, contact region 67 is placed closer to the edgeopposite to the corner and edge where gate pad 52 is placed. Thisconfiguration decreases the length of gate electrodes 28 in active area206 and increases the length of gate electrodes 28 in active area 204,which provides for a more efficient distribution of the gate resistanceload.

In one embodiment, contact region 67 is placed in an offset location ondevice 20 to reduce gate resistance in active area 206 by about one halfthe resistance of gate runner 53, and to increase gate resistance inactive area 204 by about one half the resistance of gate runner 53. Inthis embodiment, the gate resistance of active area 206 is given by:

2Rg _(FET206) +R ₅₃−(R ₅₃/2)

where Rg_(FET206) is the resistance of gate electrodes 28 in active area206 when contact region 67 is placed in the center of device 20, and R₅₃is the resistance of metal runner 53. The gate resistance of active area204 is given by:

2Rg _(FET204) +R ₅₃/2

where Rg_(FET204) is the resistance of gate electrodes 28 in active area204 when contact region 67 is placed in the center of device 20. This isan example of a predetermined placement of contact region 67 thatoptimizes the distribution of gate resistance.

In another embodiment, shield contact region 67 is the only shieldcontact used to make contact to shield electrodes 21 and is placed in aninterior portion of device 20. That is, in this embodiment shieldelectrode runners 64 and 66 are not used. This embodiment isappropriate, for example, when switching speeds are not as critical, butwhere the resurf effect of the shield electrode is desired. In oneembodiment, shield contact region 67 is placed in the center of device20. In another embodiment, shield contact region 67 is placed offsetfrom center of device 20. In these embodiments, shield contact region 67provides contact to shield electrodes 21 within or inside of trenches 22while control electrode runners 54 and 56 make contact to controlelectrodes 28 within or inside trenches 22 near edges 201 and 202. Thisembodiment further saves on space within device 20. In anotherembodiment, control electrodes 28 extend and overlap onto major surface18 and control electrode runners 54 and 56 make contact to controlelectrodes outside of trenches 22.

FIG. 3 is a top view of another embodiment of a semiconductor device,die or chip 30. In this embodiment, gate pad 52 is placed in cornerportion 238 of device 30 similar to device 20. Device 30 is similar todevice 20 except that gate runners 54 and 56 are configured to decreasethe left-to-right non-uniformity of gate resistance. In one embodiment,gate runner 56 feeds, connects, or links into an additional gate runner560 at a substantially central location 562. Gate runner 560 thenconnects to gate electrodes 28 (shown in FIG. 1) in active area 204. Inanother embodiment, gate runner 54 feeds, connects, or links into gaterunner 540 at a substantially central location 542. Gate runner 540 thenconnects to gate electrodes 28 (shown in FIG. 1) in active area 206. Itis understood that one or both of gate runners 54 and 56 can beconfigured this way. Also, if used shield contact region 67 can beoffset in device 30 as shown in FIG. 2. In one embodiment, shieldelectrode runner 66 is placed between gate runners 56 and 560 and edge201, and shield electrode runner 64 is placed between gate runners 54and 540 and edge 202. The gate runner configuration of FIG. 3 can beused as well in devices that do not include shield electrodes to reduceleft-to-right non-uniformity of gate resistance.

FIG. 4 shows an enlarged cross-sectional view of a gate/shield electrodecontact structure, connective structure, or contact structure or region40, which is taken along reference line IV-IV in FIG. 2. In general,structure 40 is a contact area where contact is made between gateelectrodes 28 and gate runners 54 and 56, and where contact is madebetween shield electrodes 21 and shield electrode runners 64 and 66. Inpreviously known gate/shield electrode contact structures, a doublestack of polysilicon or other conductive material is placed on top ofthe major surface of a substrate in peripheral or field regions of thedevice to enable contact to be made. Such double stacks of material canadd in excess of 1.2 microns to surface topography. The double stacks ofmaterial on the major surface create several problems that include asurface topography that is non-planar, which affects subsequentphotolithography steps and manufacturability. These previously knownstructures also increase die size.

Structure 40 is configured to address, among other things, the doublepolysilicon stack problem with previously known devices. Specifically,upper surface 210 of shield electrode 21 and upper surface 280 of gateelectrode 28 are both recessed below major surface 18 of semiconductormaterial 11 so that contact is made to shield electrodes 21 and gateelectrodes 28 within or directly inside of trenches 22. That is, in oneembodiment gate electrodes 28 and shield electrodes 21 do not overlap orextend on to major surface 18. A conductive structure 431 connects gaterunner 56 to gate electrode 28, and a conductive structure 432 connectsshield electrode runner 66 to shield electrode 21. Conductive structures431 and 432 are similar to conductive structures 43 as described inconjunction with FIG. 1. Structure 40 uses planarized dielectric layer41 and planarized conductive structures 431 and 432 to provide a moreplanar topography. This structure enables deep submicron lithography andglobal planarization in power device technology. In addition, thisconfiguration enables portion 444 of conductive layer 44 to wrap aroundend portion 541 of gate runner 54 (as shown in FIG. 2), and portion 446to wrap around end portion 561 of gate runner 56 (as shown in FIG. 2)and to do so without consuming too much die area.

In another embodiment, shield electrode 21 overlaps onto major surface18 and contact to shield electrode 21 is made there while gate electrode28 remains within trenches 22 without overlapping upper surface 210 ofshield layer 21 or major surface 18 and contact to gate electrode 28 ismade within or above trenches 22. This embodiment is shown in FIG. 25,which is cross-sectional view of a structure 401, which is similar tostructure 40 except shield electrode 21 overlaps major surface 18 asdescribed above. In this embodiment, shield electrodes 21 and conductivelayer 44 wrap-around end portions 541 and 561 (shown in FIG. 2) andsource metal 44 makes contact to shield electrodes 21 through openingsin dielectric layer 41.

Another feature of structure 40 is that insulator layers 24 and 27,which are thicker than insulator layer 26 (shown in FIG. 1), surroundand overly shield electrode 21 even where shield electrode 21 approachesmajor surface 18. In previously known structures, a thinner gate oxideseparates the gate electrode from the shield electrode in the field orperipheral regions. In previously known structures oxide is also thinnerat the top surface-to-trench interface where both gate shield routing ismade. However, such structures, where gate or shield oxides are thinned,are susceptible to oxide breakdown and device failure. Structure 40reduces this susceptibility by using thicker insulator layers 24 and 27.This feature is further shown in FIGS. 17-18.

Turning now to FIGS. 5-16, which are partial cross-sectional views, amethod of manufacturing structure 40 of FIG. 4 is described. It isunderstood that the process steps used to form structure 40 can be thesame steps used to form device 10 of FIG. 1 as well as the shieldingstructures described in FIGS. 20-23. FIG. 5 shows structure 40 at anearly step of fabrication. A dielectric layer 71 is formed over majorsurface 18 of semiconductor material 11. In one embodiment, dielectriclayer 71 is an oxide layer such as a low temperature deposited siliconoxide, and has a thickness from about 0.25 microns to about 0.4 microns.Next, a masking layer such as a patterned photoresist layer 72 is formedover dielectric layer 71 and then dielectric layer 71 is patterned toprovide an opening 73. In this embodiment, opening 73 corresponds to oneof many trench openings for forming trenches 22. The unmasked portion ofdielectric layer 71 is then removed using conventional techniques andlayer 72 is then removed.

FIG. 6 shows structure 40 after one of trenches 22 has been etched intosemiconductor layer 14. For perspective, this view is parallel to thedirection that trenches 22 run on devices 20 and 30. That is, in FIG. 6trench 22 runs left to right. By way of example, trenches 22 are etchedusing plasma etching techniques with a fluorocarbon chemistry. In oneembodiment, trenches 22 have a depth of about 2.5 microns, and a portionof dielectric layer 71 is removed during the process used to formtrenches 22. In one embodiment, trenches 22 have a width of about 0.4microns and can taper or flare out to 0.6 microns where, for example,conductive structures 431 and 432 are formed to electrically connectgate electrodes 28 and shield electrodes 21 to gate runners 54 or 56 andshield electrode runners 56 or 66 respectively. Surfaces of trenches 22can be cleaned using conventional techniques after they are formed.

FIG. 7 shows structure 40 after additional processing. A sacrificialoxide layer having a thickness of about 0.1 microns is formed overlyingsurfaces of trenches 22. This process is configured to provide a thickeroxide towards the top of trenches 22 compared to lower portions oftrenches 22, which places a slope in the trench. This process alsoremoves damage and forms curves along lower surfaces of trenches 22.Next, the sacrificial oxide layer and dielectric layer 71 are removed.Insulator layer 24 is then formed over surfaces of trenches 22. By wayof example, insulator layer 24 is a silicon oxide and has a thicknessfrom about 0.1 microns to about 0.2 microns. A layer of polycrystallinesemiconductor material is then deposited overlying major surface 18 andwithin trenches 22. In one embodiment, the polycrystalline semiconductormaterial comprises polysilicon and is doped with phosphorous. In oneembodiment, the polysilicon has a thickness from about 0.45 microns toabout 0.5 microns. In one embodiment, the polysilicon is annealed at anelevated temperature to reduce or eliminate any voids. The polysiliconis then planarized to form region 215. In one embodiment, thepolysilicon is planarized using a chemical mechanical planarizationprocess that is preferentially selective to polysilicon. Region 215 isplanarized to portion 245 of insulator layer 24, which is configured asa stop layer.

FIG. 8 shows structure 40 after subsequent processing. A masking layer(not shown) is formed overlying structure 40 and patterned to protectthose portions of region 215 that will not be etched such as portion217. Exposed portions of region 215 are then etched so that the etchedportions are recessed below major surface 18 to form shield electrodes21. In one embodiment, region 215 is etched to about 0.8 microns belowmajor surface 18. In one embodiment, a selective isotropic etch is usedfor this step. The isotropic etch further provides a rounded portion 216where shield electrode 21 transitions into portion 217, which extendsupward towards major surface 18. This step further clearspolycrystalline semiconductor material from exposed portions of theupper surfaces of trenches 22. Any remaining masking materials can thenbe removed. In one embodiment, portion 245 of insulator layer 24 isexposed to an etchant to reduce its thickness. In one embodiment, about0.05 microns are removed. Next, additional polycrystalline material isremoved from shield electrode 21 so that upper surface 210 of shieldelectrode 21 including portion 217 is recessed below major surface 18 asshown in FIG. 9. In one embodiment, about 0.15 microns of material isremoved.

FIG. 10 shows structure 40 after still further processing. A portion ofinsulator layer 24 is removed where portion 217 of shield electrode 21has been recessed. This forms an oxide stub structure 247, which isconfigured to reduce stress effects during subsequent processing steps.After oxide stub structure 247 is formed, an oxide layer (not shown) isformed overlying shield electrode 21 and upper surfaces of trenches 22.In one embodiment, a thermal silicon oxide growth process is used, whichgrows a thicker oxide overlying shield electrode 21 because shieldelectrode 21 is a polycrystalline material and a thinner oxide alongexposed sidewalls of trenches 22 because these sidewalls aresubstantially monocrystalline semiconductor material. In one embodimentsilicon oxide is grown and has a thickness of about 0.05 microns onsidewalls of trenches 22. This oxide helps to smooth the upper surfacesof shield electrodes 21. This oxide is then removed from the sidewallsof trenches 22 while leaving a portion of the oxide overlying shieldelectrode 21. Next, insulator layer 26 is formed overlying the uppersidewalls of trenches 22, which also increases the thickness of thedielectric material already overlying or formed on shield electrode 21to form insulator layer 27 thereon. In one embodiment, a silicon oxideis grown to form insulator layers 26 and 27. In one embodiment,insulator layer 26 has a thickness of about 0.05 microns, and insulatorlayer 27 has a thickness greater than about 0.1 microns.

FIG. 11 shows structure 40 after polycrystalline semiconductor materialhas been formed overlying major surface 18. In one embodiment, dopedpolysilicon is used with phosphorous being a suitable dopant. In oneembodiment about 0.5 microns of polysilicon is deposited overlying majorsurface 18. In one embodiment, the polysilicon is then annealed at anelevated temperature to remove any voids. Any surface oxide is thenremoved using conventional techniques, and the polysilicon is thenplanarized to form gate electrodes 28. In one embodiment, chemicalmechanical planarization is used with the oxide overlying major surface18 providing a stop layer.

Next, gate electrodes 28 are subjected to an etch process to recessupper surface 280 below major surface 18 as shown in FIG. 12. In oneembodiment, dry etching is used to recess upper surface 280 with achemistry that is selective with respect to polysilicon and siliconoxide. In one embodiment, a chlorine chemistry, a bromine chemistry, ora mixture of the two chemistries is used for this step. It is convenientto use this etch step to remove polycrystalline semiconductor from theoxide layer above surface 210 of portion 217 so that when a silicidelayer is used with gate electrode 28, it does not form above surface210, which would complicate the contacting of shield electrode 21 insubsequent process steps.

FIG. 13 shows structure 40 after silicide layer 29 has been formedoverlying surface 280. In one embodiment, silicide layer 29 is titanium.In another embodiment, silicide layer 29 is cobalt. In a furtherembodiment, a self-aligned silicide (salicide) process is used to formlayer 29. For example, in a first step, any residual oxide is removedfrom major surface 280. Then, titanium or cobalt is deposited overlyingstructure 40. Next, a lower temperature rapid thermal step (about 650degrees Celsius) is used to react the metal and exposed polycrystallinesemiconductor material. Structure 40 is then etched in a selectiveetchant to remove only unreacted titanium or cobalt. A second rapidthermal step at a higher temperature (greater than about 750 degreesCelsius) is then used to stabilize the film and lower its resistivity toform layer 29.

In a next sequence of steps, ILD 41 is formed overlying structure 40 asshown in FIG. 14. In one embodiment, about 0.5 microns of phosphorousdoped silicon oxide is deposited using atmospheric pressure chemicalvapor deposition. Next, about 0.5 microns of silane basedplasma-enhanced chemical vapor deposited oxide is formed on or over thephosphorous doped oxide. The oxide layers are then planarized back to afinal thickness of about 0.7 microns using, for example, chemicalmechanical planarization to form ILD 41. In FIG. 14, insulator layer 27and stub 247 are no longer shown within ILD 41 because they all compriseoxide in this embodiment, but it is understood that they can be presentin the final structure.

FIG. 15 shows structure 40 after trench openings 151 and 152 have beenformed in ILD 41 to expose a portion of silicide layer 29 and shieldelectrode 21. Conventional photolithography and etch steps are used toform openings 151 and 152. Next, exposed portions of shield electrode 21are further etched to recess part of portion 217 below surface 210.

Next, conductive structures or plugs 431 and 432 are formed withinopenings 151 and 152 respectively as shown in FIG. 16. In oneembodiment, conductive structures 431 and 432 aretitanium/titanium-nitride/tungsten plug structures, and are formed usingconventional techniques. In one embodiment, conductive structures 431and 432 are planarized using, for example, chemical mechanicalplanarization so the upper surfaces of ILD 41 and conductive structures431 and 432 are more uniform. Thereafter, a conductive layer is formedoverlying structure 40 and patterned to form conductive gate runner 56,shield electrode runner 66 and source metal layer 44 as shown in FIG. 4.In one embodiment, conductive layer 44 istitanium/titanium-nitride/aluminum-copper or the like. A feature of thisembodiment is that the same conductive layer is used to form sourceelectrode 44, gate runners 54 and 56, and shield electrodes 56 and 66 asshown in FIG. 2. Additionally, conductive layer 46 is formed adjacentsubstrate 12 as shown in FIG. 4. In one embodiment, conductive layer 46is a solderable metal structure such as titanium-nickel-silver,chromium-nickel-gold, or the like.

FIG. 17 is a partial top plan view of a contact or connective structure170 according to a first embodiment that is configured to provide acontact structure for making contact to gate electrodes 28 and shieldelectrodes 21 within or inside of trenches 22. That is, structure 170 isconfigured so that conductive contact to gate electrode 28 and shieldelectrode 21 can be made inside of or within trenches 22. Forperspective, connective structure 170 is one embodiment of a top view ofstructure 40 without conductive gate runner 56, shield electrode runner66, conductive structures 431 and 432, and ILD 41. This view also showsinsulator layer 26 adjacent gate electrode 28 as shown in FIG. 1.Additionally, this view shows one advantage of this embodiment. Inparticular, shield electrode 21 in connective structure 170 issurrounded by insulator layers 24 and 27, which are thicker thaninsulator layers 26. This feature reduces the oxide breakdown problemwith previously known structures, which provides a more reliable device.In this embodiment, structure 170 is striped shape and contact to bothgate electrodes 28 and shield electrodes 21 is made within a wider orflared portion 171. Structure 170 then tapers down to a narrower portion172 as it approaches, for example, the active area of the device. Asshown in FIG. 17, gate electrode 28 has a width 174 within flaredportion 171 that is wider than width 176 of shield electrode 21 withinflared portion 171. In this embodiment, end portion 173 of trench 22terminates with a shield electrode 21, which is surrounded by insulatorlayers 24 and 27, which are thicker than insulator layer or gatedielectric layer 26. In one embodiment, end portion 173 is adjacent toor in proximity to edge 201 or edge 202 of device 20 or device 30 shownin FIGS. 2 and 3.

FIG. 18 is a partial top plan view of a contact connective structure 180according to a second embodiment that is configured to provide a contactstructure for making contact to gate electrodes 28 and shield electrodes21 formed within or inside of trenches 22. That is, structure 180 isconfigured so that conductive contact to gate electrode 28 and shieldelectrode 21 can be made inside of or within trenches 22. In thisembodiment, structure 180 includes a thin stripe portion 221 and aflared portion 222 that is wider than stripe portion 221. In thisembodiment, flared portion 222 provides a wider contact portion formaking contact to shield electrode 21. Structure 180 further includesanother separate flared portion 223 that is wider than stripe portion221 for making contact to gate electrode 28. Like structure 170, shieldelectrode 21 is surrounded by insulator layers 24 and 27, which arethicker than insulator layers 26. In one embodiment, shield electrode 21includes a narrow portion 211 within stripe portion 221 and a widerportion 212 within flared portion 222. In this embodiment, insulatorlayer 24 is within flared portion 222 and further extends into thinstripe portion 221. In this embodiment insulator layer 26 is only withinthin stripe portion 221 and flared portion 223. In this embodiment, endportion 183 of trench 22 terminates with a shield electrode 21, which issurrounded by thicker insulator layers 24 and 27. In one embodiment, endportion 183 is adjacent to or in proximity to edge 201 or edge 202 ofdevice 20 or device 30 shown in FIGS. 2 and 3.

FIG. 19 is a partial top plan view of a contact or connective structure190 according to a third embodiment that is configured to provide acontact structure for making contact to gate electrode 28 and shieldelectrode 21 within or inside of trench 22. That is, structure 90 isconfigured so that conductive contact to gate electrode 28 and shieldelectrode 21 is made inside of or within trenches 22. In thisembodiment, trench 22 includes a thin stripe portion 224 and a flaredportion 226 that is wider than stripe portion 224. In this embodiment,flared portion 226 provides a wider contact portion for making contactto both gate electrode 28 and shield electrode 21. Shield electrode 21is surrounded by thicker insulator layers 24 and 27, which is thickerthan insulator layers 26. In one embodiment, gate electrode 28 includesa narrow portion 286 within thin stripe portion 224 and a wider portion287 within flared portion 226. In this embodiment, insulator layer 26 iswithin thin stripe portion 224 and further extends into flared portion226. In this embodiment, thicker insulator layers 24 and 27 are onlywithin flared portion 224. In one embodiment, shield electrode 21 iswithin flared portion 226 only. It is understood that combinations ofstructures 170, 180 and 190 or individual structures 170, 180, and 190can be used in structure 40 with devices 20 and 30. In this embodiment,end portion 193 of trench 22 terminates with a shield electrode 21,which is surrounded by with thicker insulator layers 24 and 27. In oneembodiment, end portion 193 is adjacent to or in proximity to edge 201or edge 202 of device 20 or device 30 shown in FIGS. 2 and 3.

Turning now to FIGS. 20-23, various shielding structure embodiments aredescribed. FIG. 20 shows a partial top plan view of a trench shieldingstructure 261 according to a first embodiment. Shielding structure 261is suitable for use with, for example, devices 20 and 30, and isconveniently formed using the processing steps used to form device orcell 10 and structure 40 described previously. Shielding structure 261is an embodiment of a shielding structure that runs at least partiallybelow or underneath gate pad 52 to better isolate or insulate gate pad52 from semiconductor layer 14. Structure 261 includes a plurality oftrenches 229, which are formed at least in part underneath gate pad 52.Trenches 229 are conveniently formed at the same time as trenches 22.Portions of trenches 229 are shown in phantom to illustrate that theyare underneath gate pad 52 and shield electrode runner 66.

As further shown in FIG. 21, which is a partial cross-sectional view ofstructure 261 taken along reference line XXI-XXI of FIG. 20, instructure 261 trenches 229 are each lined with insulator layer 24 andinclude a shield electrode 21. However, in one embodiment of structure261 trenches 229 do not contain any gate electrode material 28. That is,in this embodiment structure 261 does not include any gate or controlelectrodes. As shown in FIG. 20, shield electrodes 21 are connected toshield electrode runner 66, and in one embodiment are electricallyconnected to source metal 44. In another feature of the presentembodiment, ILD 41 separates shield electrodes 21 from gate pad 52 andthere are no other intervening polycrystalline or other conductivelayers overlying major surface 18 between gate pad 52 and structure 261.That is, structure 261 is configured to better isolate gate pad 52 fromsemiconductor region 11 without adding more shielding layers overlyingthe major surface as used in previously known devices. Thisconfiguration helps to reduce gate-to-drain capacitance and does sowithout extra masking and/or processing steps. In one embodiment,spacing 88 between adjacent trenches 229 in structure 261 is less thanabout 0.3 microns. In another embodiment spacing 88 is less than onehalf the depth 89 (shown in FIG. 21) of trenches 22 to provide a moreoptimum shielding. In one embodiment it was found that a spacing 88 ofabout 0.3 microns provides about a 15% reduction in gate-to-draincapacitance compared to a spacing 88 of 1.5 microns. In one embodimentof structure 261, trenches 229 and shield electrodes 21 do not pass allof the way below gate pad 52. In another embodiment, structure 261 andshield electrodes 21 pass all of the way the past gate pad 52. In astill further embodiment, gate pad 52 contacts gate electrode 28 at anedge portion 521 of gate pad 52 as shown in FIG. 20.

FIG. 22 shows a partial top plan view of a trench shielding structure262 according to a second embodiment. Structure 262 is similar tostructure 261 accept that structure 262 is placed to pass a plurality oftrenches 229 and shield electrodes 21 below or underneath gate pad 52and gate runner 53 to further isolate gate pad 52 and gate runner 53from semiconductor layer 14. In one embodiment of structure 262, contactis made to shield electrodes 21 at both shield electrode runners 64 and66 as shown in FIG. 22, which are further connected to source metal 44.Structure 262 is configured to better isolate gate pad 52 and gaterunner 53 from semiconductor region 11. In structure 262, a portion oftrenches 229 pass all the way past or underneath at least a portion ofgate pad 52. That is, in one embodiment at least one trench 229 extendsfrom at least one edge or side of gate pad 52 to another opposing edgeof gate pad 52.

FIG. 23 shows a partial top plan view of a trench shielding structure263 according to a third embodiment. Structure 263 is similar tostructure 261 accept that structure 263 is placed to pass a plurality oftrenches 229 and shield electrodes 21 below or underneath gate pad 52and at least a portion of gate runner 56. In one embodiment, a portionof trenches 229 and shield electrodes 21 below gate runner 56 pass allthe way below or past gate runner 56. In another embodiment, a portionof trenches 229 and shield electrodes 21 below gate runner 56 only passa part of the way below gate runner 56. In another embodiment, a portionof gate runner 56 makes contact to gate electrodes 28 at an edge portion568 as shown in FIG. 23. Structure 263 is configured to better isolategate pad 52 and at least a portion of gate runner 56 from semiconductorlayer 14. It is understood that all, one or combinations of structures261, 262, and 263 can be used with, for example, devices 20 and 30.

FIG. 24 shows a partial top plan view of structure 239 from device 20shown in FIG. 2. As shown in FIG. 24, conductive layer 44 includesportion 446, which wraps around end 561 of gate runner 56 and connectsto shield electrode runner 66 where contact is made to shield electrodes21. FIG. 24 further shows an example of the location of trenches 22 andgate electrodes 28 where contact is made between gate runner 56 and gateelectrode 28. Additionally, FIG. 24 shows trenches 22 having a stripedshape and extending in a direction from the active area where conductivelayer 44 is to the contact area where gate runner 56 and shield runner66 are located. It is understood that the connective structures of FIGS.17, 18 and 19 can be used with structure 239 either individually or incombination. Structure 239 further illustrates an embodiment thatprovides for the use of one metal layer to connect the variousstructures.

In summary, a shielding structure for a semiconductor device has beendescribed. The structure includes a plurality of trenches withpassivation liners and shield electrodes, which are placed on or withinthe semiconductor device in locations to improve isolation and reducecapacitance effects. In one embodiment, the shielding structure isplaced beneath a control pad. In another embodiment, the shieldingstructure is placed beneath a control runner. The shielding structureeliminates intervening conductive layers, which have been in previouslyknown structures. This reduces manufacturing costs and complexity. Theshielding structure uses structures similar to those used for formsemiconductor devices with trench shield electrodes, which simplifiesintegration.

Although the invention has been described and illustrated with referenceto specific embodiments thereof, it is not intended that the inventionbe limited to these illustrative embodiments. Those skilled in the artwill recognize that modifications and variations can be made withoutdeparting from the spirit of the invention. Therefore, it is intendedthat this invention encompass all such variations and modifications asfall within the scope of the appended claims.

We claim:
 1. A semiconductor device structure comprising: a region ofsemiconductor material having a first major surface; a first trenchstructure formed in an active area of the semiconductor device, whereinthe first trench structure includes a first trench, a first controlelectrode, and a first shield electrode; a control pad formed overlyingthe first major surface and coupled to the first control electrode; anda second trench structure formed in the region of semiconductor materialunderlying at least a portion of the control pad, wherein the secondtrench structure includes a second trench, an insulator layer and asecond shield electrode, and wherein the second shield electrode and thefirst shield electrode are coupled together, and wherein the secondtrench structure is configured as a shielding structure to isolate thecontrol pad from the region of semiconductor material.
 2. The structureof claim 1, wherein the second trench structure includes a plurality oftrenches, wherein the plurality of trenches has a trench spacing lessthan about 0.3 microns.
 3. The structure of claim 1, wherein thestructure is absent any intervening conductive layers between the secondtrench structure and the control pad.
 4. The structure of claim 1,wherein the second trench structure is formed absent a controlelectrode.
 5. The structure of claim 1 further comprising a firstcontrol runner connecting the control pad to the first controlelectrode, wherein the second trench structure is further formedunderlying at least a portion of the first control runner.
 6. Thestructure of claim 1, wherein the second trench extends from a firstside of the control pad to another side of the control pad opposite tothe first side.
 7. The structure of claim 1, wherein the first andsecond shield electrodes are coupled together with a shield electroderunner overlying the first major surface.
 8. The structure of claim 7,wherein the second shield electrode does not overlap the first majorsurface, and wherein the shield electrode runner makes contact to thesecond shield electrode inside of the second trench.
 9. The structure ofclaim 1, wherein the second trench structure includes a plurality oftrenches each having a depth, wherein the plurality of trenches arespaced a distance less than about one-half the depth.
 10. The structureof claim 1, wherein the control pad makes direct contact to the firstcontrol electrode underneath a portion of the control pad.
 11. Thestructure of claim 1 further comprising a dielectric layer between thecontrol pad and the second trench structure.
 12. A semiconductor devicestructure comprising: a region of semiconductor material having a majorsurface and first and second opposing edges; a first trench formed inthe region of semiconductor material extending in a direction from thefirst edge to the second edge; a first shield electrode formed in thefirst trench; a first control electrode formed in the first trench; asecond trench formed in the region of semiconductor material; aninsulator layer formed in the second trench; a second shield electrodeformed in the second trench overlying the insulator layer; a control padoverlying at least a portion of the second trench, wherein the controlpad is coupled to the first control electrode; and a first shieldelectrode runner formed overlying the major surface, wherein the firstshield electrode runner is coupled to the second shield electrode. 13.The structure of claim 12, wherein the first shield electrode is coupledto the second shield electrode adjacent the first edge, and wherein thestructure further comprises a second shield electrode runner coupled tothe second shield electrode adjacent the second edge.
 14. The structureof claim 12 further comprising: a control electrode runner connectingthe control pad to the first control electrode; a third trench formed inthe region of semiconductor material below at least a portion of thecontrol electrode runner; and a third shield electrode formed in thethird trench, wherein the second and third trenches are formed absentcontrol electrodes.
 15. The structure of claim 14 further comprising adielectric layer overlying the second and third trenches, wherein thecontrol pad overlies the dielectric layer.
 16. A semiconductor devicestructure comprising: a region of semiconductor material having a firstmajor surface; a first trench structure formed in an active area of thesemiconductor device, wherein the first trench structure includes afirst trench, a first control electrode, and a first shield electrode; acontrol pad formed overlying the first major surface and coupled to thefirst control electrode; a second trench structure formed in the regionof semiconductor material underlying at least a portion of the controlpad, wherein the second trench structure includes a second trench, aninsulator layer and a second shield electrode, and wherein the secondshield electrode and the first shield electrode are coupled together,and wherein the second trench structure is formed absent a controlelectrode; and a dielectric layer formed between the control pad and thesecond trench structure.
 17. The structure of claim 16, wherein thesecond trench structure includes a plurality of trenches each having adepth, wherein the plurality of trenches are spaced a distance less thanabout one-half the depth.
 18. The structure of claim 16 furthercomprising a first control runner connecting the control pad to thefirst control electrode, wherein the second trench structure is furtherformed underlying at least a portion of the first control runner. 19.The structure of claim 16, wherein the structure is formed absent anyconductive layers overlying the major surface between the control padand the second trench structure.
 20. The structure of claim 16, whereinthe first shield electrode is coupled to the second shield electrodewith a first shield electrode runner adjacent the first edge, andwherein the structure further comprises a second shield electrode runnercoupled to the second shield electrode adjacent the second edge.
 21. Amethod of forming a semiconductor device comprising the steps of:providing a region of semiconductor material having a major surface andfirst and second opposing edges; forming a first trench in the region ofsemiconductor material extending in a direction from the first edge tothe second edge; forming a first shield electrode in the first trench;forming a first control electrode in the first trench; forming a secondtrench in the region of semiconductor material; forming an insulatorlayer in the second trench; forming a second shield electrode in thesecond trench overlying the insulator layer; forming a control padoverlying at least a portion of the second trench, wherein the controlpad is coupled to the first control electrode; and forming a firstshield electrode runner overlying the major surface, wherein the firstshield electrode runner is coupled to the second shield electrode.